This document discusses a Modern Design Method of using Programmable Logic Devices (PLDs) to Synchronise either its own INTERNAL LOGIC FUNCTIONS or EXTERNAL DEVICES:-

Internal Logic Functions

Functions like the SHIFT REGISTER possesses the SYNCHRONOUS LOAD SIGNAL to control data flow. This has different functionality depending on its logic level:

External Devices

Traditionally, Parallel Bus Devices like A/D Converters and Static RAMs were interfaced to a microprocessor and controlled by its software.

High Speed PLDs can achieve the same result by emulating the microprocessor's CONTROL SIGNALS.

They have several advantages:

• Higher Data Bandwidth
• Higher Pin Count
• Reduced Component Count

Higher data bandwidth is achieved as PLDs can control the external devices directly and don't require slow sequential microprocessor instructions to function.

Higher Pin Count

Field Programmable Gate Arrays (FPGAs) are one of the PLD family that can be chosen with ENOUGH pins to feed ALL the external device needs.

e.g. A 32 KByte Static RAM would need a considerable number of dedicated control lines:

• 15 Address Pins
• 8 Data Pins
• A Chip Select Pin
• A Write Enable Pin

• Single Chip with NO Address/Data/Control Bus where the I/O pins have MANY Dedicated Multiple Functions.

 
• Expanded Address/Data/Control Bus where most of the pins are dedicated to bus signals, leaving only the FEW remaining pins for direct I/O control.

To control A/Ds and RAMs with programmable logic you need a SEQUENCER circuit DESCRIBED BELOW to co-ordinate their TIMING signals.

Reduced Component Count

Using a SINGLE FPGA with ENOUGH I/O pins for ALL FUNCTIONS reduces:

• Component Count
• Printed Circuit Board:
• Surface Area
• Complexity
• Costs

Intellectual Property is the name given to the highest descriptive level of a circuit function. This means that you can design complex circuits at a CONCEPTUAL LEVEL where you don't have to include all the detail.

An Example:

The information about the COUNTER FUNCTION or its IP is reduced to a few simple statements:

• How many bits wide (WIDTH = 4)
• How to count up or down (UPDOWN I/P signal)
• What number to count up to or down to (MODULUS = 10)

All the common functions like Shift Registers, Multiplexers and Adders are described in the same way. These will be available in the design tool.

The I/P (data[ ]) and O/P (q[ ]) DATA is specified as a BUS of a certain WIDTH. Control signals like Synchronous Load (SLOAD) to parallel load the data and Asynchronous Clear (ACLR) to reset the function's O/Ps to Zero are all OPTIONAL.

ALTERA FPGA devices are supported by their MaxPlus II graphical design tool. Their IP functions are called MEGA-FUNCTIONS.

XILINX FPGA devices on the other hand have a similar design tool that supports IP design and that's called X-BLOX. This name is quite appropriate as you're actually designing at the CONCEPTUAL LEVEL where the circuit is a simple BLOCK DIAGRAM.

BOTH companies support a WIDE range of IP FUNCTIONS. All the standard functions are included in their packages. The more complex IP Functions like MICROPROCESSORS may also be included.

There are MANY companies that sell IPs or CORES as they're also known. The more POPULAR the devices are, the HIGHER the cost will be. I was quoted recently a Z80 MICROPROCESSOR for £50,000. Less popular devices like UARTs were around the £5,000.

However, SEARCHING the WEB you'll find Sites offering FREE cores:-

The circuit below describes how the control signals are created using the IP Method described above:

The circuit example above was created using Altera's MaxPlus II Design Tool, but the concept can be adapted to ANY design tool as described above.

How it Works

• The WHOLE circuit is SYNCHRONOUS, being driven by a SINGLE EXTERNAL CLOCK. (the CLK signal in the example above) 

 
• The STATE[7..0] is a shortcut for a BUS signal and represents 8 Signals: STATE0, STATE1, through to STATE7. The STATE0 signal represents the Least Significant Bit. 

 
• As the COUNTER counts up, the STATE O/Ps of the DECODER become active IN SEQUENCE. e.g. when COUNTER VALUE = 4 : the STATE4 Signal is Active - when COUNTER VALUE = 5 : the STATE5 Signal is Active. N.B. ONLY ONE STATE IS ACTIVE AT A TIME and ALL OTHERS WILL BE INACTIVE.

 
• The STATE signals are then connected to either the "J" or "K" I/P of the J-K FLIP FLOPS.

 
• The Flip Flop O/Ps will then remain in that particular STATE until changed by an ACTIVE STATE signal connected to one of its J or K I/Ps.


N.B. 2 particular STATES of the J-K Flip Flop's TRUTH TABLE are IMPORTANT here:
 
• When J AND K are BOTH ONE:

 
• Normally this would TOGGLE the O/P but as described above the DECODER CAN'T create this condition because only ONE of its O/Ps can be ACTIVE at a time.

 
• When J AND K are BOTH ZERO:

 
• This condition CAN occur as the DECODER may be outputting a STATE that's NOT directly connected to EITHER the J or K I/Ps. However the TRUTH TABLE states that if BOTH J AND K I/Ps are ZERO the O/P remains UNCHANGED.

 
• The Flip Flop O/Ps then become the TIMING SIGNALs for EITHER other INTERNAL CIRCUITRY or EXTERNAL DEVICES connected to the PLD.

• Counter
• Decoder
• Flip Flops

• The counter's MODULUS is the MAXIMUM NUMBER the counter counts to BEFORE looping back through zero.

• The WIDTH is set to a number that exceeds the MODULUS. e.g. If the MODULUS is set to 235 it would need an 8 Bit Counter to achieve this. ( i.e. 7 Bits = 127 : 8 Bits = 255 )

• Therefore the HIGHER NUMBER of WIDTH = 8 is chosen to ensure the count value required is REACHABLE.

• The decoder translates its I/Ps into STATEs. There is ONE O/P node for EVERY possible state.

• The 3 I/Ps generate 8 O/P States. Only ONE O/P will be active at a time - the one that represents the 3 Bit I/P Number.

• The decoder's WIDTH setting MUST be set to the SAME as the COUNTER's WIDTH.

• The DECODES parameter is always set to 2^WIDTH i.e. 2^3 = 8

• J-K Flip Flops are used with their  "J" and "K" I/Ps connected to various STATE O/Ps of the DECODER.

• ALL the J-K Flip Flop's CLOCK I/Ps are connected together. ( The CLK signal in this example )

• The Flip Flop O/Ps represent the CONTROL SIGNALs required
  ( CTRL1, CTRL2 and CTRL3 in this example )

Simulation is used to evaluate circuit FUNCTIONALITY. The circuit I/Ps are STIMULATED with signals you define and the simulator CREATES the effective O/P signals from your circuit definition.

Your task is then to COMPARE the O/P signals created by the simulator with your PREDICTIONS.

The DIFFERENCES represent ERRORS somewhere in your design.

The simulation of the sequencer circuit is shown below:

• The counter's O/Ps (SEQ[2..0]) ALWAYS CHANGE STATE on the RISING EDGE of the counter's CLOCK Signal (CLK). 

 
• The counter COUNTS UP from STATE0 to STATE5, (6 States in Total)  RESETS to ZERO then repeats.

 
• Signals CTR1, CTRL2 and CTRL3 are being set HIGH or LOW by the STATE SIGNALS that are connected to their associated J-K Flip Flop I/Ps.

 
• The Control Signal CTRL3 is only ACTIVE for ONE CYCLE so in fact the J-K Flip Flop is REDUNDANT! Therefore Signal CTRL 3 could come from an INVERTED STATE 0 Signal DIRECTLY.

I develop new experiments and teaching aids for my department. The latest of these is described in detail by CLICKING HERE.

The microcontroller used in this project DOESN'T have any EXTERNAL Address/Data/Control Busses.

However the design required that students SHOULD have experience in interfacing to EXTERNAL devices, where the Address, Data and Control Busses appear on I/O pins of the microcontroller.

Therefore the FPGA's task is to create a PHYSICAL Address/Data/Control Bus with all the correct TIMING so that interfacing to the unit's external devices like Static RAM and D/A Converters can occur as if the microprocessor actually had it's OWN Address/Data/Control Bus.

The circuit described above is simple to understand and implement by using the GRAPHICAL DESIGN TOOLS described. However the principle can ALSO be adapted for use with Hardware Description Languages like VHDL.

The TIMING in COMPLEX designs is usually the MOST DIFFICULT part to implement. However, using SIMULATION enables the circuit TIMING to be continuously EVALUATED, DOCUMENTED and MODIFIED VISUALLY, THROUGHOUT the whole design process.

Nowadays, ALL External Device TIMING SPECIFICATIONS are described GRAPHICALLY in their DATA SHEETS. Therefore using SIMULATION with this CIRCUIT TECHNIQUE makes this difficult task MUCH EASIER.

The SIMPLIFIED EXAMPLE described above demonstrates the PRINCIPLES which are FULLY EXPANDABLE for use in the control of MORE COMPLEX designs.

And Finally:

The method described above of using INTELLECTUAL PROPERTIES is a VERY POWERFUL TOOL particularly when used in the design of COMPLEX circuits.

The way it SIMPLIFIES designs is AMAZING!

TRY IT - I'm SURE you'll AGREE.